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Itanium®– a viable next-generation technology for crash simulation?

Adrian Hillcoat Hewlett-Packard Ltd Bracknell, UK In the area of crash simulation, LS-DYNA has traditionally been a good application for measuring performance of leading computer architectures. This paper considers the architectural design of the Intel Itanium® processor, as well as the system architectures into which Itanium fits, with the purpose of understanding the benefits of the novel 64-bit EPIC architecture over and above conventional 64-bit RISC architectures as well as 32-bit Intel XEON processor architectures. The paper will provide details of LS-DYNA performance results achieved using distributed memory parallel execution. It will conclude with a look into the future to predict what might be achievable with further generations of this processor architecture for crash codes.